In recent years, memory interface specifications have been significantly updated to meet the increasing requirements for high-speed processing. Joint Electron Device Engineering Council (JEDEC) defines standards for the requirements of linearity for post drivers of memory circuits. A post driver is utilized to adjust a voltage level of an input/output (I/O) driver circuit, and to compensate the impedance of the I/O driver circuit so as to alleviate the effect of reflection waves. Moreover, a post driver is utilized to improve the integrity of output signals of the I/O driver circuit. According to JEDEC's standards, in a given direct-current (DC) bias condition, the effective turn-on resistance (RON) of a post driver needs to fall within certain ranges. As the JEDEC's standards migrate from double data rate third generation (DDR3), double data rate fourth generation (DDR4) to low power double data rate fourth generation (LPDDR4), the allowable ranges of effective RON of the post driver have been further narrowed down.